i-MOS case study

i-MOS Semiconductors: Review of business plan

Summary: I will not to fund them at this stage.

I-MOS semiconductors is proposing a solution to the important problem of thermal power dissipation in CMOS circuits. This problem is expected to get worse with increasing power density.  On the face of it, their solution, which is based on patenting certain implementations of impact ionization for CMOS circuits seems very promising.

However, it is clear based on some background research, that they cannot get coverage around the principle of impact ionization itself. Impact ionization is the process in a material by which one energetic charge carrier can lose energy by the creation of other charge carriers. For example, in semiconductors, an electron (or hole) with enough kinetic energy can knock a bound electron out of its bound state (in the valence band) and promote it to a state in the conduction band, creating an electron-hole pair.

If this occurs in a region of high electrical field then it can result in avalanche breakdown. This process is exploited in avalanche diodes, by which a small optical signal is amplified before entering an external electronic circuit. In an avalanche photodiode the original charge carrier is created by the absorption of a photon.

The application of this to the design of CMOS devices appears to be the novel aspect of their IP.

A closer analysis of the business plans's technology, risks & mitigation sections along with the projections regarding financials leaves me somewhat concerned.

The part about the management team's inexperience would be a easy concern to raise - but given the potential of mitigating this by leveraging Stanford University's links to the Silicon Valley, it may be less of a real challenge.

My real concerns rest more with the area that they speak about IP but do not clarify how broad the IP is. If the IP covers specific implementation of i-MOS it may be less valuable than if it covers all possible approaches to implementing i-MOS.

Their own business plans speak to how they will have to use series A for technology development and IP generation. Does this imply insufficient IP coverage?

One of their key technical risk is that the technology itself depends on strained silicon. The IP for strained silicon is held by IBM. If strained silicon technology development or rollout is slow, this will their business plan. They have no control over this. 

They also have a market risk since the number of potential customers is fairly small and these customers will hold pricing power during negotiations. This will result in the company being a "price taker" putting at risk its financials. If foundries fail to adopt their process, their backup plan going from IP licensing model to product oriented SRAM or DRAM company will require 100 orders of magnitude higher levels of investment in a very cyclical and capital intensive industry. This is not really a credible mitigation strategy.

Their financial risk is high since relatively few successful semiconductor IP companies have been successful and high levels of investment are needed in this area. Their stated mitigation for producing relatively simple product based on the fundamental technology doesn't seem to be well thought out.

My assessment is that they are in a very early part of the technology development curve and need to incubate their ideas a bit more before seeking venture funding.

I would choose not to fund them at this stage.